NIST · ИТ · 30e56df41bd1b98ea261
A depth-16 circuit for the AES S-box
New techniques for reducing the depth of circuits for cryptographic applications are described and applied to the AES S-box. These techniques also keep the number of gates quite small. The result, when applied to the AES S-box, is a circuit with depth 16
NIST · ИТОфициальный источник · 2011-06-17
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"title_en": "A depth-16 circuit for the AES S-box",
"designation": "",
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"date": "2011-06-17",
"date_original": "June 17, 2011",
"url": "https://www.nist.gov/publications/depth-16-circuit-aes-s-box",
"source": "NIST Publications",
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"authors_en": "Joan Boyar, Rene Peralta",
"abstract_excerpt_en": "New techniques for reducing the depth of circuits for cryptographic applications are described and applied to the AES S-box. These techniques also keep the number of gates quite small. The result, when applied to the AES S-box, is a circuit with depth 16",
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"title_en": "A depth-16 circuit for the AES S-box",
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"authors_en": "Joan Boyar, Rene Peralta",
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