f89c7d63bebbdc1dd020 · Logic Minimization Techniques with Applications to Cryptology
Logic Minimization Techniques with Applications to Cryptology
A new technique for combinational logic optimization is described. The technique is a two-step process. In the rst step, the non-linearity of a circuit as measured by the number of non-linear gates it contains is reduced. The second step reduces the number
{
"title_en": "Logic Minimization Techniques with Applications to Cryptology",
"designation": "",
"series": "",
"status": "",
"date": "2013-04-01",
"date_original": "April 1, 2013",
"url": "https://www.nist.gov/publications/logic-minimization-techniques-applications-cryptology",
"source": "NIST Publications",
"display_en": "",
"authors_en": "Joan Boyar, Philip Matthews, Rene Peralta",
"abstract_excerpt_en": "A new technique for combinational logic optimization is described. The technique is a two-step process. In the rst step, the non-linearity of a circuit as measured by the number of non-linear gates it contains is reduced. The second step reduces the number",
"id": "f89c7d63bebbdc1dd020",
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{
"title_en": "Logic Minimization Techniques with Applications to Cryptology",
"designation": "",
"series": "",
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"date": "2013-04-01",
"date_original": "April 1, 2013",
"url": "https://www.nist.gov/publications/logic-minimization-techniques-applications-cryptology",
"source": "NIST Publications",
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"authors_en": "Joan Boyar, Philip Matthews, Rene Peralta",
"abstract_excerpt_en": "A new technique for combinational logic optimization is described. The technique is a two-step process. In the rst step, the non-linearity of a circuit as measured by the number of non-linear gates it contains is reduced. The second step reduces the number"
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